Each die on this semiconductor wafer features early radiation-hardening-by-design techniques.

Designing Integrated Circuits to Withstand Space Radiation

Donald C. Mayer and Ronald C. Lacoe

The high cost of maintaining dedicated foundries to create space electronics has motivated an exploration of alternatives for next-generation space systems. One approach in particular—the use of design techniques to mitigate the effects of space radiation on integrated circuits—is gaining wider acceptance.

The market for satellite components is small compared with the consumer microelectronics market, and manufacturers of integrated circuits have very little incentive to develop parts specifically for space applications. This presents a problem for satellite designers because space electronics must operate in an environment that is vastly different from what is seen on Earth. Space electronics are continually bombarded by energetic plasmas, particles, and other forms of radiation from the sun and galactic sources. This radiation can cause unpredictable spacecraft anomalies, and mission success can depend on how well the onboard electronics resist its effects. Components specifically designed to tolerate this environment are said to be "radiation hardened," or simply "rad hard."

During the past three decades, several companies have developed manufacturing processes to produce a range of rad-hard electronic products. These processes are somewhat different from the ones used in commercial foundries because they include a few modified process steps that produce circuits with greater radiation resistance. These parts are more expensive than their commercial counterparts and have lagged several generations behind in terms of processing speed, power, and size. Moreover, many companies that were in the business of supplying rad-hard components a decade ago have dropped out of the market. Only two remain active today.

This graph charts the increasing speed of microprocessors versus year of introduction for commercial products (the diamond plots) and rad-hard products (the square plots). Because of the additional effort and cost associated with developing radiation-hardened processes, the performance of space-qualified electronics has typically lagged by 5 to 7 years behind their nonhardened counterparts. Similar performance lags are seen in memories, application-specific integrated circuits, and other electronic components.

Faced with rising costs and decreasing availability of space-qualified electronic parts, designers have been searching for alternatives to the traditional dedicated rad-hard foundry approach. One strategy in particular has been gaining popularity in recent years. Known as radiation hardening by design (RHBD), this approach relies solely on circuit design techniques to mitigate the damage, functional upsets, and data loss caused by space radiation.

Aspects of this approach have been in use for some time, but most frequently in combination with dedicated rad-hard manufacturing facilities. More recently, a number of research institutions and corporations have demonstrated the basic feasibility of RHBD using standard commercial foundries; however, to satisfy the military's need for a wide range of part types and hardness levels, a self-sustaining RHBD infrastructure must be established, and the RHBD approach must be proven robust enough to use without some degree of fabrication process control. Aerospace is working to develop this infrastructure while demonstrating the efficacy of design-hardening techniques.

Major Concerns

Two types of space radiation are of particular concern for spacecraft electronics designers. The first, known as the total ionizing dose, represents the cumulative effect of many particles hitting a device throughout the course of its mission life, slowly degrading the device until it ultimately fails. The second involves high-energy particles that penetrate deep into materials and components, leaving a temporary trail of free charge carriers in their wake. If these particles hit vulnerable spots in the circuit, they can produce adverse effects, described generically as "single-event effects."

One type of electronic component often found aboard a satellite is the complementary metal-oxide semiconductor (CMOS) integrated circuit. CMOS devices use the simultaneous flow of both electron and hole currents through transistors and logic gates. (A "hole" is a quantum mechanical concept that is generally modeled as a "missing" electron in the semiconductor lattice.) The transistors that carry these negative and positive currents need to be isolated from each other; this is where space radiation can interfere.

Total Dose Effects

The manufacturing processes used to build commercial electronic components in the 1970s and 1980s were severely inadequate to meet the needs of the space community. But as commercial CMOS processes have advanced, the inherent radiation resistance of these devices has improved—and thus, the RHBD approach has become more feasible. For example, the current that flows through CMOS transistors is governed by a low-voltage gate over each device, isolated by a layer of oxide. These insulating layers can develop a charge after long exposure to ionizing radiation, and this charge can affect the flow of current through the device; but as circuits have shrunk, the thicknesses of these insulating layers have decreased, presenting less opportunity for charge buildup.

Charge buildup affects the current-voltage characteristics of the transistors used in semiconductor circuits. Proper operation of a transistor relies on the ability to switch it from a low-conductance (off) state to a high-conductance (on) state as the gate voltage passes through a threshold. Extended exposure to radiation can shift the threshold voltages (top image), making the transistors easier or harder to switch. Radiation may also increase the leakage current (bottom image), causing the on and off states of the transistors to become less distinguishable. Either effect can ultimately cause circuit failure.

More problematic are the radiation-induced increases in leakage current—unregulated current flowing across unintended areas of the semiconductor. When leakage current bypasses the transistor's isolated regions, it degrades the distinguishability of the transistor's "on" and "off" states. Leakage also increases the circuit's background current, or the amount of current flowing when the device is in a quiescent state. Such an increase, multiplied by the tens of millions of switches in each circuit, can drive up power consumption, increasing heat-dissipation needs and prematurely draining the power source of the satellite. In an extreme case, the isolation between discrete components can also be lost, rendering the circuit useless.

The edges of the transistors where the thin gate oxide abuts the much thicker field oxide, which covers and insulates the border regions of the semiconductor, are also prone to leakage in a radiation environment. The process traditionally used to manufacture the transistor borders can induce significant material stress, which may facilitate the increase in leakage current when exposed to radiation. The newest isolation-oxide manufacturing processes impart less stress and seem to have achieved a greater inherent radiation resistance.

Edge-current leakage in transistors. Current should flow only between the source and the drain when the gate receives a proper voltage; however, after extended exposure to ionizing radiation, current can leak through at the edges, where the gate oxide and insulating field oxide meet (view larger image).

Aerospace has been testing the total-dose hardness of various commercially available CMOS manufacturing processes since 1995 by building test devices and irradiating them in a cobalt-60 radiation chamber (see sidebar, Testing Total-Dose Hardness). The latest results are encouraging. In some tests, several commercial CMOS devices withstood more than 100 kilorads of total-dose radiation, which is adequate for some space missions. Still, this level of inherent total-dose hardness may not be sufficient for many space applications. In these cases, additional immunity can be obtained using RHBD techniques.

For example, Aerospace and other companies have shown that total-dose effects can be mitigated by designing transistors in an enclosed shape, thereby eliminating the edges that can trigger current leakage along the borders of conventional transistors. Current flows from the center to the outside of these devices, making them immune to edge leakage current, but requiring a larger area for each transistor. Furthermore, transistor-to-transistor leakage can be reduced by incorporating guard bands around individual transistors or groups of transistors. Other novel techniques are being applied to conventional transistor switches to boost their immunity to total ionizing dose radiation. These techniques consume area in the design, thereby reducing the total number of transistors available for a given circuit function and increasing the capacitance, and thus the power consumption, of the circuit. The trade-off may be worthwhile: Using RHBD, several researchers have demonstrated radiation hardness in excess of 20 megarads using commercial CMOS foundries, making them suitable for use in nuclear reactors as well as severe space environments.

Single-Event Effects

While the hardness of CMOS circuits to total-dose effects has been improving, some single-event effects are becoming more problematic. Single-event effects occur when energetic particles penetrate the semiconductor, creating temporary "wires" of charge that produce spurious currents at critical circuit locations. When these particles strike sensitive nodes in the circuit, various adverse effects can occur, ranging from data upset to latchup or burnout.

RHBD techniques have shown some efficacy in mitigating particle-induced effects. For example, single-event latchup can occur when adjacent negative-current and positive-current transistors become shorted together through the current induced by an energetic particle. Aerospace tests indicate that this effect can be easily prevented using guard bands around adjacent devices. These guard bands, consisting of doped "trenches" in the silicon, greatly increase the current needed to trigger and sustain latchup, making these types of events much less likely in space.

Single-event upsets require different mitigation techniques. Single-event upsets occur when energetic particles deposit charge into memory circuits, causing stored data to change state (from a "1" to a "0," for example). As circuits shrink and transistor volumes become smaller, the total charge needed to cause an upset in a circuit element decreases. Thus, even protons moving through the circuit may deposit sufficient charge to disrupt sensitive locations. Susceptibility to single-event upsets can be reduced by increasing the amount of charge needed to trigger a bit flip or by providing feedback resistors that give the circuit time to recover from a particle strike. Perhaps the most common approach is to use redundant information storage or error-checking circuitry. For example, a technique known as "voting logic" can be used to catch and correct potential errors in latches. With this technique, a single latch does not effect a change in bit state; rather, several identical latches are queried, and the state will only change if the majority of latches are in agreement. Thus, a single latch error will be "voted away" by the others.

Potential errors in latches can be caught and corrected using voting logic, in which a majority of the outputs of three identical latches determines the correct output. Two simultaneous errors must occur to produce an error at the output, which is rare in a properly designed circuit.

Another technique useful for overcoming single-event upsets is known as "error detection and correction." In this technique, the system architecture provides extra check bits in each stored word in memory; when these extra bits are read and interrogated, errors become apparent and can be corrected. Perhaps the simplest approach would be to insert a single bit that denotes whether the content of a word has an even or odd parity; this requires minimal overhead, but does not automatically identify the location of any observed errors. On the other hand, to uniquely detect and correct a single error in a 16-bit word using the common "Hamming code" method requires the insertion of six additional bits. Thus, the error detection and correction technique requires a significantly greater number of memory bits to store a given amount of information.

Performance Implications

Design-hardened versions of integrated circuits require more space or circuitry than their unhardened counterparts; therefore, overall performance will not be as good. Depending on the specific circuit function and the level of hardness required, the area penalty may vary widely. Different mixes of RHBD techniques can be used to provide elements with a range of hardness levels, allowing the circuit designer to target different radiation requirements. Critical memory-storage elements such as latches and flip-flops might require hardening against total-dose effects as well as single-event upset. These elements may require redundant transistors and may consume three or four times the area of a conventional element. In fact, the static random-access memory, which contains primarily storage elements, is the worst-case circuit for the RHBD approach. On the other hand, combinational elements such as logic gates or multiplexers may require only total-dose hardening, with a smaller area penalty, or may even employ commercial designs as is, if the total-dose requirements are modest. The area penalty for a given circuit layout will depend on the overall number of each of these types of elements.

A six-transistor latch, commonly used as the storage element in a static memory circuit, is shown alongside a design-hardened 12-transistor variant (Calin et al.). "B" and "BN" are the bit lines, used to input and output zeros and ones to the memory cell. "W" represents the word line, used to activate the cell and read out the stored information. In the conventional cell, a particle strike directly into node Q may cause the latch to change state, resulting in an error. In the design-hardened version, Q is represented at two different nodes. Thus, a strike at any single node cannot cause an upset. The number of transistors per latch has doubled, which can significantly reduce the available gate count in a given circuit area.

For example, a design-hardened chip using two-, three-, or four-input logic gates with edgeless transistors and guard bands might be several times bigger than a commercial version of the chip. The resulting capacitance increase would cause an increase in power consumption and a reduction in circuit speed, compared with a commercial design using the same technology. But, compared with the same chip from a typical rad-hard foundry, which is assumed to be two generations behind the commercial process, the design-hardened part would show improvements in area, power, and speed.

Reliability

The shrinking of commercial CMOS technologies has proceeded faster than reductions in supply voltages. As a result, each new generation operates with relatively higher electric fields. This has exacerbated the reliability problems associated with advanced CMOS devices because the higher electric fields can damage materials and interfaces. Manufacturers of commercial systems have been willing to trade reliability for better overall performance, but designers of space systems cannot accept this trade-off. Space systems require higher reliability because replacement of faulty parts is difficult or impossible after deployment and because component failures may compromise national security. Furthermore, typical service life tends to be longer for military systems.

Various approaches can help mitigate the reduced reliability of advanced CMOS technologies. For example, power-supply voltages can be lowered to reduce internal electric fields in a given circuit. A system-level approach to power management might include controls to cut power to unused circuits or subcircuits, thereby prolonging service life. The use of RHBD techniques offers even more options. For example, the length of critical transistor gates can be increased to reduce electric fields and prolong service life; however, because these longer transistors are slower than the minimum-size transistors, the increase in reliability comes at the expense of speed. Another alternative is the use of annular transistors to reduce the drain electric field in advanced CMOS devices. An analysis performed by Aerospace has demonstrated that the curvature associated with these annular devices spreads the electric field lines at the high-field end of the transistor, reducing the damage done by energetic carriers.

Future Issues

The RHBD approach must demonstrate its ability to consistently and reliably supply a full range of rad-hard parts before it will be accepted as a viable alternative to the dedicated foundry approach. Aerospace is working with the relevant government agencies to create and maintain a coordinated RHBD infrastructure to address all the relevant issues.

For example, circuit designers use computer-aided design tools to define and verify the final circuit layout, to perform logical simulation of the design, to identify potential failure modes, and to perform static and dynamic timing simulations. These tools use so-called "cell libraries" to simplify the design process as much as possible. Each library is a collection of individual circuit elements that includes functional and performance information about each element. Effective use of RHBD requires that knowledge of the behavior of the circuits in the space environment be incorporated into the computer-aided design tools. For instance, the programs would need to simulate the electrical behavior of the transistor switch in a radiation environment based on the structure of the device and the physics of the radiation interactions.

Rad-hard cell libraries must be developed and maintained that will include provisions for reliable operation in harsh environments. A number of cell libraries will probably be needed for each CMOS generation to meet the needs of a range of space programs operating in various orbits, and with a range of reliability, survivability, and cost requirements. Funding for libraries with the most stringent requirements—and thus the smallest markets—must be generated by the customer community, most likely the Department of Defense (DOD).

Commercial foundries typically provide the starting material for all electronic components manufactured in their processing facilities; however, nonstandard starting materials incorporating epitaxial layers or insulating substrates, for example, may enhance radiation immunity. The part supplier and the selected foundry may agree to substitute appropriate starting materials to provide additional levels of radiation hardness.

Each foundry typically uses proprietary procedures developed over many years; however, nonstandard processing steps involving, for example, novel implants or modifications of layer thicknesses may help enhance radiation immunity. In an approach known as coprocessing, the RHBD part supplier and the selected foundry may agree to substitute or augment appropriate manufacturing steps to provide additional levels of radiation hardness. This approach has been used successfully by at least one rad-hard component supplier.

Government agencies, corporations, and universities around the world are presently researching and developing RHBD techniques. The Air Force Research Laboratory is funding several such projects, including some geared toward developing rad-hard digital and mixed-signal circuits. The Defense Threat Reduction Agency is similarly funding various RHBD efforts, including programs to develop a radiation-tolerant static-memory chip using a commercial foundry, a radiation-hardened readout integrated circuit using both traditional rad-hard foundry processing and RHBD techniques, and a submicron-level chip incorporating RHBD features. The agency is also developing an integrated, foundry-independent rad-hard digital design center and has a program to develop and demonstrate an analog standard cell library.

DARPA (the Defense Advanced Research Projects Agency) has recently announced a major program to develop digital, analog, and mixed-signal circuits in highly advanced commercial technologies using RHBD techniques. Aerospace will play various consulting, testing, and integration roles in this program.

NASA has also been employing design-hardening concepts in various projects. The Europa satellite, for example, will be exposed to more than 6 megarads over the life of the mission. To meet this high total-dose requirement, NASA is using rad-hard processors along with several digital and analog circuits designed using redundancy and other RHBD techniques.

Aerospace is working with each of the DOD agencies and NASA through the Radiation Hardened Electronics Oversight Council to develop and coordinate a road map that will identify funding needs and opportunities for RHBD cell libraries, design tools, component designs, test facilities, and other aspects of the RHBD infrastructure.

Summary

Radiation hardness by design has quickly evolved from a laboratory curiosity to a business strategy that may well redefine the way electronic components are procured for defense space systems. Aerospace and others have demonstrated that RHBD techniques can provide immunity from total-dose and single-event effects in commercially produced circuits. CAD tools that can model these radiation effects and cell libraries that use a range of these techniques have been developed at a number of government agencies, universities, and private companies during the past several years, culminating in the commercial production of RHBD memories, microprocessors, and application-specific integrated circuits that are being specified in DOD and NASA missions. The infrastructure needed to make RHBD a mainstream procurement approach is gradually being developed. Aerospace continues to play a major role in assessing radiation immunity trends in the commercial CMOS sector and in coordinating the development of the infrastructure needed to support RHBD for future space systems.

Further Reading

• D. R. Alexander, D. G. Mavis, C. P. Brothers, and J. R. Chavez, "Design Issues for Radiation Tolerant Microcircuits in Space," 1996 IEEE Nuclear and Space Radiation Effects Conference (NSREC) Short Course, V-1 (1996).
• G. Anelli, M. Campbell, M. Delmastro, F. Faccio, S. Florian, A. Giraldo, E. Heijne, P. Jarron, K. Kloukinas, A. Marchioro, P. Moreira, and W. Snoeys, "Radiation Tolerant VLSI Circuits in Standard Deep Submicron CMOS Technologies for the LHC Experiments: Practical Design Aspects," IEEE Transactions on Nuclear Science, Vol. 46, pp. 1690–1696 (1999).
• T. Calin, M. Nicolaidis, and R. Valazco, "Upset Hardened Memory Design for Submicron CMOS Technology," IEEE Transactions on Nuclear Science, Vol. 43, pp. 2874–2878 (1996).
• R. C. Lacoe, J. V. Osborn, R. Koga, S. Brown, and D. C. Mayer, "Application of Hardness-By-Design Methodology to Radiation-Tolerant ASIC Technologies," IEEE Transactions on Nuclear Science, Vol. 47, pp. 2334–2341 (2000).
• J. V. Osborn, R. C. Lacoe, D. C. Mayer, and G. Yabiku, "Total-Dose Hardness of Three Commercial CMOS Microelectronics Foundries," IEEE Transactions on Nuclear Science, Vol. 45, pp. 1458–1463 (1998).

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