Current commercial state-of-the-art semiconductor devices range in size from 250 to 90 nm. Some fabrication facilities are rapidly moving toward 60- and 45-nm features in their device structures. As an example, the half-pitch dimensions of dynamic random-access memory (DRAM) are expected to be 45 nm by the year 2010 and 18 nm by 2018. Similarly, application-specific integrated circuit (ASIC) feature sizes are expected to be less than 25 nm by 2010 and less than 10 nm in 2018. Oxide thicknesses are expected to follow suit and shrink to less than 1 nm by 2006. Other devices such as quantum wells range in thickness from a few to a few tens of nanometers. Clearly, the impact of defects on geometries on this scale will most certainly become more critical with respect to manufacturability and reliability of these devices. New and innovative uses of advanced analytical techniques are needed that allow imaging, visualization, and detailed examination of every part of the features of interest at the nanoscale, i.e., viewing in 3‑D with nanometer resolution.