2006 Proceedings

Microelectronics Reliability & Qualification Workshop

Wednesday, December 6, 2006

Welcome and Opening Remarks
Ronald Lacoe, Workshop Chair, The Aerospace Corporation, Yuan Chen, Technical Program Chair, JPL

Keynote Presentation I
Microelectronics Qualification Challenges for Robotic Space Missions, Richard Brace, Chief Project Assurance Manager, JPL

Session I: Reliability Challenges for Advanced Technologies

Session Chair: Harald Schone, Jet Propulsion Laboratory

1. Reliability Assessment for New Technologies: Advanced Transistor Gate Stacks, Gennadi Bersuker, Sematech
2. Characterizing Negative Bias Temperature Instability in Advanced Gate Dielectrics, John Suehle, NIST
3. Copper / Low k Dielectric Interconnects: Integration and Reliability, Glenn Alers, Novellus Systems
4. SiC pn-gated Field Effect Transistor for Extreme Temperatures, Mike Mazzola, SemiSouth
5. Packaging for High Speed Digital Electronics, Andrew Shapiro, JPL

Session II: Memory and ESD

Session Chair: Don Mayer, Aerospace

1. A Manufacturable and Embeddable Non-Volatile Memory for High Temperature and High Reliability Applications Ð Development and Characterization Information, Mammen Thomas and Jagdish Pathak, MEMTEK, LLC
2. ESD Tester Issues from a Design Engineering Standpoint, E. Worley, Silicon Crossing, Inc

Session III: Radiation Effects on Microelectronics

Session Chair: Dave Alexander, Air Force Research Laboratories

1. Modeling Single Event Effects in Advanced CMOS Processes, Jeff Black, Vanderbilt University
2. TID effects in Deep Submicron, Bulk CMOS: Effects, Mechanisms, and Modeling, Hugh Barnaby, Arizona State University
3. Prospects for Ultra-low Power Radiation Hardened by Design VLSI, Larry Clark, Arizona State University
4. A Technical and Cost Perspective for Radiation Testing Challenges, Ken LaBel, NASA Goddard SFC

Thursday, December 7, 2006

Keynote Presentation II
Silicon Technology Trends: Reliability Challenges and Opportunities, Jose Maiz, Intel Fellow, Director of Logic Technology Q&R, Intel

Panel Discussion: Advanced Technology Reliability Impact on Product Qualification Methodology
Session Chair: Yuan Chen, Jet Propulsion Laboratory
Lynett Wintergard, AMIS, Jose Maiz, Intel, Mark Porter, Medtronics, and Doug Sheldon, JPL

Session IV: FPGA Applications

Session Chair: Jon Osborn, Aerospace

1. Application Specific Qualification of FPGAs for Space Application, Doug Sheldon, JPL
2. FPGA Conversion to ASIC: Turning Convenience into a More Reliable Product, Terry Danzer, AMIS

Session V: Product Reliability and Qualification

Session Chair: Mark White, Jet Propulsion Laboratory

1. Medical Device Reliability and Qualification, Mark Porter, Medtronics
2. Improving Lifetime Prediction for Scaled CMOS Technologies using Physics-of-Failure Reliability Approach, Mark White, The Jet Propulsion Laboratory
3. Reliability Update on the Aeroflex ViaLinkTM FPGA, Bob Bauer, Aeroflex

Session VI: Advanced Packaging Technologies

Session Chair: Reza Ghaffarian, JPL

1. Extreme High Temperature Packaging, Pat McCluskey, University of Maryland
2. Embedded Flip Chip on Flex, Linda Del Castillo, JPL
3. Electronics and IC Packaging Trends, Reza Ghaffarian, JPL